Parasitic capacitance of a field effect transistor reduces the performance of the transistor by reducing the switching speed. Specifically, the capacitive coupling of a gate electrode to adjacent circuit components limits the rate at which the voltage of the gate electrode may be changed. The delay in the changes in the gate voltage due to the capacitive coupling with adjacent circuit components is then reflected in an increase in a turn-on time and a turn-off time of the field effect transistor.
All transistors with a gate electrode, including metal oxide semiconductor field effect transistors (MOSFETs), are prone to this type of parasitic capacitive coupling to adjacent circuit components by design. Particularly, highly scaled MOSFETs, in which contact vias to the source and drain regions are located close to the gate electrode, suffer from high parasitic capacitance between the gate electrode and the contact vias due to their physical proximity.
A gate stack including a high-k gate dielectric (a gate dielectric having a dielectric constant of more than 4.0, and typically more than 7.0) and a metal gate is a promising structure for continuing scaling of complementary metal oxide semiconductors (CMOS). A replacement gate process can be used to form such high-k metal gates. In a replacement gate process, a sacrificial gate electrode is formed first and is then replaced with a gate stack including a high-k gate dielectric and a metal gate. As a result of this process, the high-k gate dielectric is present along the sidewalls of the metal gate. The high value of the dielectric constant of the high-k gate dielectric affects parasitic capacitance adversely since the parasitic capacitance is proportional to the dielectric constant of the material between the gate electrode and the contact vias. Thus, it is desirable to incorporate a lower-k value spacer adjacent to the high-k gate dielectric spacer for highly scaled replacement gate CMOS. However, even conventional low-k materials (such SiCN, SiCBN) have k values of at least about 5. Further, such low-k materials suffer from the release of carbon during spacer etch processing or during subsequent source/drain activation annealing.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with reduced parasitic capacitance. Further, it is desirable to provide integrated circuits and methods for fabricating integrated circuits with high-k metal gates formed by replacement gate processes that provide for self-aligned contacts and reduced parasitic capacitance. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.